The Characteristics and Modeling of the Deep Sub-micron CMOS Device and Applications for RF Circuits Design

• Main Authors: Chien-Chih Ho, 何建志
• Other Authors: Yi-Jen Chan
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/54069297996717566227

博士 === 國立中央大學 === 電機工程研究所 === 92 === With the technological advances, the MOS device size was already scaling down to the nano dimension. The low cost of fabrication and the possibility of placing both analog and digital circuits on the same chip so as to improve the overall performance made CMOS technology attractive. The scaling down of device improves the speed of MOSFETs significantly and hence the silicon CMOS technologies have been widely recommended and used in the wireless front-end transceiver for its high integration level, low cost, and potential of low-power operation. To achieve these goals, the accurate device model and detailed device characteristics are important for the circuit designers. Although, the p-channel MOSFETs suffer for their low transport properties; however, the lower 1/f noise level and less hot carrier effect in pMOS may provide an unique solution in microwave circuit design. Therefore, in order to design a rf circuit based on the pMOS, a modified 0.18 ?m pMOS rf large-signal model based on conventional BSIM3v3 model is proposed in the Chapter II, which demonstrated a well prediction of the dc, S-parameters, large-signal characteristics and power performance. We also designed a 2.4 GHz fully integrated pMOS voltage-controlled oscillator to verify our modified rf large-signal model. In the Chapter IΙI, a self-defined large-signal model for 0.13 ?m nMOS transistor is proposed. The self-defined model can predict not only dc and microwave performance well but also in noise characteristics by using P, R, C noise parameters calculation. Besides the simplified and accurate model of the device is needed, the optimum gate layout of 0.13 ?m transistors for high frequency and power application becomes a critical issue, which is also investigated in this chapter. In addition, the optimum gate layout of n+/n-well MOS varactor for the tuning range and Q factor improvement is also studied in this chapter. Besides the 0.13 ?m device high frequency and power performances, one of the key features of a technology platform for rf applications is the noise performance, particularly for front-end receiver functions. The noise performance of the optimized gate layout structure in constant total gate-width devices, different gate length and gate width devices are investigated in Chapter IV. We also design two VCOs by different gate layout MOSFETs to verify the phase noise influence from device layout structure. In the Chapter V, various rf circuits are presented based on the home-made modified rf large-signal model and implemented by 0.18 ?m CMOS technologies, which include low phase noise 2.4 GHz fully integrated pMOS VCO, 2.4 GHz/5.2 GHz dual-band VCO and high power-added efficiency class-E amplifier. The pMOS VCO including inversion-mode varactors and on-chip spiral inductors, achieves an excellent phase noise of –101 dBc/Hz at a 100 KHz offset and figure-of-merit of –177 dBc/Hz. In the dual-band VCO design, the switching transistors concept used in the tank circuit realizes the dual-band VCO operation, which provides the oscillation frequency bands for both 2.4 GHz and 5.2 GHz applications. In the efficient amplifier design, the switching operating mode class-E amplifier delivers 17.3 dBm output power at 2.4 GHz, with a maximum PAE of 63% from a 2-V supply voltage. Furthermore, the class-E amplifier with a class-F driver stage demonstrates the improved maximum PAE of 70%.