Design and Implementation of Low Jitter Logic Blocks

• Main Authors: Chang-Hsiao Tsai, 蔡昌孝
• Other Authors: Shyh-Jye Jou
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/23475292915783548484

碩士 === 國立中央大學 === 電機工程研究所 === 92 === In the thesis, we first analyze the jitter of digital circuits. We divide the jitter source into four categories: vdd / gnd bounce jitter, substrate noise jitter, data dependent jitter, and clock jitter. For the frequently used flip-flop and MUX, we propose an architecture that has the least jitter. Also, sizing and layout techniques are used to decrease the jitter. In general, the measurement results of output waveform jitter consists of several kinds of jitter. For the D-flip-flop we propose an architecture that could accumulate the output jitter, except for clock jitter so that the output waveform mainly consist of output jitter, except for clock jitter. Design results show that the low-jitter architecture can achieve only 1.17ps and 0.04ps (peak-peak) for D-flip-flop and MUX respectively, using TSMC 0.18um CMOS technology.