| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 92 === In the thesis, we focus on sigma delta modulator in single loop second order multi-bits architectures, and build a design model for one. There is a main objective which designer can obtain related parameter and accomplish scheme of circuitry faster. In addition, the most important part of design model is accurate estimation of SNR equation. During the scheme, designer will not obtain accurate parameter (ex. OSR, B) if designer use ideal SNR equation to estimate. We can also use simulation of software, but it can’t obtain relation between devices and result of simulation; the problems in SNR equation are also discussed completely. We will modify the SNR equation by systematically analyzing the device noises and incorporate their effects into the SNR equation.
At lastly of the thesis, we present the design model of sigma delta in single loop second order multi-bits architecture which provide the information of numbers of switch, numbers of capacitor, considerations of quantizer and design flow; besides, modify the ideal SNR equation which incorporate the device noise.
|
|---|
