Study on the Junction Isolation of Power Integrated Circuits

• Main Authors: Chien-Jen Su, 蘇建仁
• Other Authors: Lon-Kou Chang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/feg28j

碩士 === 國立交通大學 === 電機與控制工程系所 === 92 === Since Power Integrated Circuit( PIC ) combines power devices with low voltage CMOS logic circuits on the same chip, it offers more intact function, and cheaper cost. However, the cross-talk happens between the power device and CMOS circuits or between one power device and the others. Therefore, the development of the isolation technology is indispensable in the power integrated circuit design. This thesis studies the junction isolation functions held between the power devices and CMOS logic circuits. The N-type and P-type guard ring are used to be the isolation structure. MEDICI, a 2-D device simulator, is used to simulate the relation of the leakage current between the layout parameters and the bias of the isolation structure when the power device is in forward bias and reverse bias, respectively. The design parameters of the layout include the width of P-sink, the distance between devices, and the changes of the widths of the N-type and P-type guard ring. We have simulated and analyzed variety of isolation performance resulted in the changes of the layout parameters and the bias of the isolation structure. Finally, we propose the most proper isolation design for each combination of high and low power devices.