| Summary: | 碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === Abstract
In this thesis, we propose a digital modulator with FSK, DFSK, BPSK and QPSK function by using direct digital frequency synthesizer (DDFS). For DDFS, the spur item were caused by finite output word length, phase truncation and sine/cosine mapping function (SCMF) are also presented. The initial guess and error correct ROM table are used to approximate the sine function, Initial guesses techniques using 2-segment line approximation. In order to reduce the ROM size, the ROM memory was partitioned into two ROM blocks. Coarse ROM (384 bits) and fine ROM (192 bits) were explored. The total size of ROM table is 576 bits. Only adder circuits were required in the additional circuits. No subtractor and multiplier were needed. Simulation shows that the worst case of SFDR (spurious free dynamic range) is 61dBC for various output frequency. When we compared with other same spec DDFS, Rom table size and additional circuits are smallest, but under sacrificing the performance of SFDR. The proposed DDFS is used to implement the digital modulator with FSK, DFSK, BPSK and QPSK function; the digital modulator is also with sine/cosine output. Using Synplify Pro to synthesize the verilog code and Altera device EPF10K100ARC240-1 to verify the function of digital modulator; it share the 238 logic elements (4%) and 1152 bits (2%) memory with device.
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