Study and DSP Implementation of IEEE 802.16a TDD OFDM Downlink Synchronization

• Main Authors: Tsung-Shu Chiang, 蔣宗書
• Other Authors: David W. Lin
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/16540436963565992513

碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === This thesis presents an implementation method of IEEE 802.16a TDD (time division duplex) OFDMA (frequency-division multiple access) downlink (DL) synchronization techniques. The DL synchronization includes symbol time synchronization, fractional frequency offset synchronization, integer frequency offset synchronization and frame synchronization. Our implementation is software-based, employing Texas Instruments’ TMS320C6416 digital signal processor (DSP) housed on Innovative Integration's Quixote cPCI card. We implement the complete 802.16a DL system to verify the accuracy of synchronization function. The computation on this system is fixed-point for obtaining a higher execution efficiency. The data format we use in synchronization is Q.15 which is a 16 bits fixed-point data format that consists of a sign bit nad 15 fractional bits. We use the assembly-optimized FFT which is supported by TI’s DSP library to obtain the high execution efficiency. We increase the execution efficiency of synchronization by using intrinsics of C6416 DSP and unrolling the disqualified loops to make the software pipeline well scheduled. The efficiency is much increased after we refine the program. The execution efficiency of synchronization is analyzed. We find that the real time operation requirement is over the synchronization execution time. If we want the synchronization function to achieve real-time speed, we must partition the synchronization function into sub-functions and implement these functions either on more DSPs or on FPGA.