THE DESIGN OF HIGH-OUTPUT-POWER RF POWER AMPLIFIER USING MOS DEVICES WITH POSITIVE SUBSTRATE BIAS
碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === This thesis is proposed for designing a high-output-power RF CMOS power amplifier using MOS devices with positive substrate bias. This design is targeted on the standard of FCC 15.247. The MOS devise with positive substrate bias was used to reduce the device...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/01425454375502701902 |
| Summary: | 碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === This thesis is proposed for designing a high-output-power RF CMOS power amplifier using MOS devices with positive substrate bias. This design is targeted on the standard of FCC 15.247. The MOS devise with positive substrate bias was used to reduce the devices size and relative parasitic capacitance. Furthermore, it’s helped that the driver stage can deliver large enough signal to output stage and improve the efficiency. To consider the linearity and efficiency, the input stage operates in class-A and output stage operates in class-AB. The differential with cascade topology is used to alleviate the gate-drain breakdown phenomenon. Besides, stability enhanced circuits are used to ensure that the design can operate in unconditional stable.
This chip is fabricated in a standard 0.25μm single-poly-five-metal CMOS process. There are no oscillated phenomenon during experiment. Experimental results showed this chip can provide 25.3 dBm output power with 17.51% PAE at input power equal 0dBm at 26.2˚C. The 1dB compression gain is -9 dBm and the ACPR is -43.07dBc at 400kHz frequency when used GSM(1.8GHz) modulated signal as input.
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