CMOS Programmable Gain Amplifier Design for Dual Band 802.11a-802.11b Wireless Network System

• Main Author: 李嘉富
• Other Authors: 溫瓌岸
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/67482978266906712816

碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === The purpose of this thesis is to design and simulate a reliable circuit suit for Dual-Band 802.11a-802.11b wireless network system to realize a programmable gain amplifier, which includes the advantages of high-bandwidth, low-noise, DC-Offset-Cancellation feature and easy to control the gain setting. Using four Gain-Amplifier casecade architecture on circuit achieves the system requirement that the gain range is 0~60dB, with 1dB gain step. Input referred noise at high-gain mode is only 6.5nV/sqrtHZ, and bandwidth up to 125MHz. The proposed circuit simulates with Agilent ADS tool, and the circuit is implemented with UMC 01.8um 1P6M CMOS process. The verification values approaches to the simulation results. It consumes only 3.73mW from a 1.8V supply voltage (includes 4-stage Gain-Amplifier, related bias circuit and DC-Offset-Cancellation circuit; the 3.3V output drive circuit is not include). The consumption of power-down mode is 3.6uW and die occupies 0.01mm2. In sum, this work presents a low-noise and high-bandwidth PGA circuit for a low cost, low power, and high-integration solutions.