Design of CMOS RF Synthesizer for 802.11a

• Main Author: 潘宏良
• Other Authors: 溫瓌岸
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/42611797040681696389

碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === The radio frequency circuit of nowadays attract lots of researches hot subject that countless scholars wants to develop, various types of thesis made under the very challenge CMOS process had succeed to have VCO characteristic fit the wireless network specification. However, it is a hard study if you would like the easy interfered radio frequency circuit combine successfully with digital cirtcuit frequency synthesizer to a single of chip. The design is fabricated in UMC 0.18um 1P6M CMOS process to make frequency synthesizer, according to IEEE802.11a WLAN of 5GHz U-NII specification. The chip adopts 20 pin QFN package and uses RO4003 substrate circuit's board examine the signal. Usign L-C tank VCO structure of the circuit in order to get the low phase noise and prevent temperature and process variations, we added switched capacity network circuit to increase frequency tunning range. After examining, the tunning range is 22%, and phase noise is -88.87dBc/Hz@100KHz, and outputs frequency is 3421MHz- 4177MHz. In addition the circuit also includes reference frequency circuit, phase detect circuit, charge pump circuit, low pass filter circuit and frequency divider circuit. All these circuits can function work normally through measurements. In order to make the output frequency of the VCO as low as reference frequency, we use the structure of the integer-N divider to get carrier frequency in this thesis. The integer-N divider can choose channel frequency and the phase settling time is 145uS after testing. This thesis also proposes dual mode frequency synthesizer based on 802.11a WLAN structure that can be adapted to 2.4GHz 802.11b WLAN.