The Design of a Parallel Data Path with Dynamic Power Management

• Main Author: 王志軒
• Other Authors: 闕河鳴
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/5b6vmz

碩士 === 國立交通大學 === 電信工程系所 === 92 === Very long instruction word (VLIW) processor is a multi-issue processor with many functional units. In recent research [1-3], many VLIW processors can provide the functions of baseband digital signal processing (DSP) calculations such as discrete cosine transform (DCT), finite impulse response (FIR) filter, and motion estimation. These general purpose DSP calculations are very common in platform-based design and reconfigurable architecture for wireless communications and multi-media applications. So if a VLIW processor is applied as the microprocessor in platform-based design or reconfigurable architecture, some general purpose DSP blocks can be replaced by VLIW processor and the design complexity of hardware in platform-based design and reconfigurable architecture can be reduced. However, power dissipation in VLIW processor can be a serious problem due to the low code density and hardware utilization. In this thesis we applied dynamic power management techniques in the 16-bits parallel data path which is similar to a data path in a three-issue VLIW processor to reduce the overhead of power dissipation. Two dynamic power managements: clock gating and voltage separation are chosen since they are suitable for the parallel data path. Clock gating can reduce the power dissipation caused by low code density in pipeline registers and voltage separation can reduce power wastage in functional units that is caused by low hardware utilization. Furthermore, we also explored an appropriate design flow for these two power managements with current electronic design automation (EDA) tool. All the design and verification are completed with UMC 0.18 um process. Power analysis is accomplished with five test benches. The power dissipation of the parallel data path is successfully reduced and the power and performance of the data path become scalable as we expected. A VLIW processor with such a data path is provided as a good option for microprocessor in platform-based design and reconfigurable architecture.