| Summary: | 碩士 === 國立交通大學 === 電信工程系所 === 92 === Abstract
This thesis studies the feasibility of Zero Pin Integrated Circuit (ZP-IC). ZP-IC, being unrestricted by the power cord, can substantially reduce chip area, and has no need to replace the battery. It is very flexible in practical applications. We find that the structure of amorphous silicon solar cells/MIM capacitor/ASIC is able to solve the power problem in ZP-IC. Three structures: the sequential discharge partial voltage capacitor, the parallel discharge partial voltage capacitor and the dynamic partial voltage capacitor are proposed, which can enable efficient use of electric power. By the simulation results, we make sure that the structures we proposed reach the expected performance, as the working time greatly lengthening. Furthermore, we propose the idea of All-capacitor transformer by taking advantage of the partial discharging capacitor. Finally, based on our study, we conclude that integrating amorphous silicon solar cells; IrDA and ASIC is the most promising scheme to realize the idea of ZP-IC.
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