Design and Implementation of 802.11a/g OFDM-Based Outer Receiver
碩士 === 國立交通大學 === 電子工程系所 === 92 === In this thesis, an IEEE 802.11a/g OFDM-based outer receiver design and implementation is presented. This proposed outer receiver consists of four modules. They are “Demapping”, “Deinterleaver”, “Depuncture”, and “Decoder” (Viterbi decoder), respectively. Viterbi D...
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ndltd-TW-092NCTU54270962019-05-15T19:38:01Z http://ndltd.ncl.edu.tw/handle/377w8u Design and Implementation of 802.11a/g OFDM-Based Outer Receiver 802.11a/g正交分頻多工外部接收器之設計與實現 Chia-Hsin Lin 林佳欣 碩士 國立交通大學 電子工程系所 92 In this thesis, an IEEE 802.11a/g OFDM-based outer receiver design and implementation is presented. This proposed outer receiver consists of four modules. They are “Demapping”, “Deinterleaver”, “Depuncture”, and “Decoder” (Viterbi decoder), respectively. Viterbi Decoder is the main function module. According to IEEE 802.11a/g, the convolutional code 1/2 is the base coding rate. Through adopting the puncture scheme, the 802.11a/g transceiver owns several data rates. Therefore, Viterbi decoder of outer receiver needs to be modified with its structure. We also discuss the soft decision resolution and traceback-length to get the optimized solution between performance and complexity. The chip is fabricated in 0.18 um CMOS process, and the maximum throughput rate can achieve 67Mbps under clock rate 25MHz. The power consumption is below 78.83mW under 1.8V. 溫瓌岸 2004 學位論文 ; thesis 71 en_US |
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碩士 === 國立交通大學 === 電子工程系所 === 92 === In this thesis, an IEEE 802.11a/g OFDM-based outer receiver design and implementation is presented. This proposed outer receiver consists of four modules. They are “Demapping”, “Deinterleaver”, “Depuncture”, and “Decoder” (Viterbi decoder), respectively. Viterbi Decoder is the main function module. According to IEEE 802.11a/g, the convolutional code 1/2 is the base coding rate. Through adopting the puncture scheme, the 802.11a/g transceiver owns several data rates. Therefore, Viterbi decoder of outer receiver needs to be modified with its structure. We also discuss the soft decision resolution and traceback-length to get the optimized solution between performance and complexity. The chip is fabricated in 0.18 um CMOS process, and the maximum throughput rate can achieve 67Mbps under clock rate 25MHz. The power consumption is below 78.83mW under 1.8V.
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author2 |
溫瓌岸 |
author_facet |
溫瓌岸 Chia-Hsin Lin 林佳欣 |
author |
Chia-Hsin Lin 林佳欣 |
spellingShingle |
Chia-Hsin Lin 林佳欣 Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
author_sort |
Chia-Hsin Lin |
title |
Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
title_short |
Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
title_full |
Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
title_fullStr |
Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
title_full_unstemmed |
Design and Implementation of 802.11a/g OFDM-Based Outer Receiver |
title_sort |
design and implementation of 802.11a/g ofdm-based outer receiver |
publishDate |
2004 |
url |
http://ndltd.ncl.edu.tw/handle/377w8u |
work_keys_str_mv |
AT chiahsinlin designandimplementationof80211agofdmbasedouterreceiver AT línjiāxīn designandimplementationof80211agofdmbasedouterreceiver AT chiahsinlin 80211agzhèngjiāofēnpínduōgōngwàibùjiēshōuqìzhīshèjìyǔshíxiàn AT línjiāxīn 80211agzhèngjiāofēnpínduōgōngwàibùjiēshōuqìzhīshèjìyǔshíxiàn |
_version_ |
1719091748832018432 |