High speed、LVDS transceiver

• Main Author: 蕭聖文
• Other Authors: 吳錦川
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/vvbqyz

碩士 === 國立交通大學 === 電子工程系所 === 92 === As the size of the LCD monitor is being enlarged and demands on the resolution, data transmission between display card in computers and a LCD monitor becomes larger and larger. So, the key of high display quality will dramatically depend on the speed of the transmission interface. Although parallel ports can achieve the goal of high speed transmission, it takes more cost and space and, sacrifices convenience. Therefore, the novelty and high-speed serial ports become a maim stream. LVDS-interface techniques are more widely used in the transmission field. It has high speed, low power, low EMI. The thesis is to design a transceiver for LVDS transmission interface. Transceiver is fabricated in 0.35um 2P4M process. Power supply is 3.3V. The transmitter makes use of a 7-phase PLL and a multiplexer to transfer parallel data to serial data. The measured jitters of the PLL output are 11.7 ps (r.m.s.) and 80 ps (peak-to-peak) at 142.8MHz. Transmitter transmits 1 Gb/s serial data normally and total power is 162mW. Receiver uses 3X-sampling skills to overcome time-skew problem. It uses the comparator with hysteresis to amplify incoming small signal to full swing, and then uses three samplers to sample data. The receiver calibrates the sampling phase after receiving sixteen data to make sure the receiver can work correctly.