Instruction Scheduling with Less Power Consumption for Nested Loop on DSP Architecture
碩士 === 國立交通大學 === 資訊工程系所 === 92 === Because portable devices become popular, digital signal processing on images and real-time data are more and more important. How to process data correctly in real-time is one of the most interesting topics to be investigated. The instruction scheduling is an impor...
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| Format: | Others |
| Language: | en_US |
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2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08816679129581424571 |
| Summary: | 碩士 === 國立交通大學 === 資訊工程系所 === 92 === Because portable devices become popular, digital signal processing on images and real-time data are more and more important. How to process data correctly in real-time is one of the most interesting topics to be investigated. The instruction scheduling is an important step through the whole process. Under resources constraints, we use retiming technique to design a method named Bottom Retiming Scheduling Method. It overcomes the shortcoming of Relax Push-Up Scheduling Method which is a bigger maximum retiming depth. Besides data throughout, low power consumption is another important issue for portable devices. Based on Bottom Retiming Scheduling Method, we integrate the operand sharing technique which can reduce switching activities to design another method named Bottom Retiming with Operand Sharing Method for low power scheduling. The experimental results show the effectiveness of these methods.
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