| Summary: | 碩士 === 國立交通大學 === 資訊工程系所 === 92 === Clustering is a well-known technique to improve the implementation of register file on VLIW processors. Without clustering, high demands on read/write ports will bring many issues on power dissipation, area and delay, and thus makes the hardware scalability problematic. However, most inter-cluster communication models rely on extra read/write ports to access register values between clusters.
The objective of the thesis is to propose an inter-cluster communication model which demands no extra read/write ports but using a kind of single-way special register. We evaluated the performance by hand-optimized codes and code rewriting generation approach. Simulated results showed that for several generic computation kernels, only a few extra cycles and special registers will be needed, but sacrificing no extra delay on register file access. Thus improvements on execution time can be achieved. The design will also benefit from less power dissipation and fewer silicon area, making the approach an efficient and economic communication scheme for clustered VLIW processors.
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