ESD protection circuit design for broadband RF circuits

• Main Authors: Bing-Jye Kuo, 郭秉捷
• Other Authors: Ming-Dou Ker
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/66271258825451743916

碩士 === 國立交通大學 === 電子工程系 === 92 === The aim in this thesis is to design the ESD protection circuits which are suitable in broadband RF circuits. The ESD protection ability and the influence to the performance of the broadband RF circuit after inserting the ESD protection circuit needs to be considered simultaneously. This thesis includes three topics, which were verified through 3 individual chips. In the first topic, a new distributed ESD protection structure is proposed to achieve both good ESD and RF performance. The proposed decreasing-size distributed ESD (DS-DESD) protection circuit is constructed by arranging ESD protection stages with decreasing device-size and separating them by the coplanar waveguides with ground shield (CPWG). The scheme is not only beneficial to the broadband RF performance, but also to the ESD protection ability (human-body-model (HBM) ESD protection level over 8 kV). In the second topic, as a π model in ac analysis, the proposed π-model distributed ESD (π-DESD) protection circuit, composed of one pair of ESD components near the I/O pin, the other pair close to the core circuit, and a CPWG connecting these two pairs, can successfully achieve both the great ESD protection ability (HBM ESD level over 8 kV) and excellent broadband RF impedance match. In the third topic, two distributed ESD protection structures are presented and applied to DAs. Fabricated in a standard 0.25-μm CMOS process, the DA with the first ES-DESD protection structure, contributing extra 300 fF parasitic capacitance to the circuit, can sustain the HBM ESD level of 5.5 kV, the machine-model (MM) ESD level of 325 V and the charged-device-model (CDM) ESD level of 500 V, and exhibits the flat-gain of 4.7 ± 1 dB over the bandwidth from 1 to 10 GHz. With the same amount of the parasitic capacitance, the DA with the second DS-DESD protection achieves a better ESD robustness, the HBM ESD level over 8 kV, the MM ESD level of 575 V and the CDM ESD level of 650 V, and performs the flat-gain of 5.0 ± 1.1 dB over the bandwidth from 1 to 9 GHz. With these two proposed ESD protections, the broadband performances of the DAs are acceptable, yet the ESD protection abilities are excellent.