Design for Flexible In-Place Viterbi Decoder with Very Low Interconnection Overheads

• Main Authors: Chun-Min Huang, 黃軍閔
• Other Authors: Ming-Der Shieh
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/58633920023402636221

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === 　　Of the key techniques to successfully designing the Viterbi decoders, how to efficiently manage the path metric memory and at the same time to minimize the interconnection networks between the memory and add_compare_select unit (ACSU) is always a key concern of hardware implementation. In this thesis, we first derive a systematic method for conflict-free address arrangement of in-place path metric update according to the butterfly-based computation. In this manner, we can increase the equivalent memory bandwidth at the expense of more complicated interconnects. To further reduce the interconnect overhead, we present a novel and efficient in-place scheduling technique, denoted as the extended in-place scheduling, such that every ACSU will only access a dedicated, partitioned memory bank; therefore, the interconnection network is simplified and the bank becomes conceptually local to the specific ACS. The resulting architecture has the following　characteristics: (1) The whole memory can be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific ACS. (2) The P partition memory banks can be merged into only two pseudo-banks regardless of the number of ACS operations. This not only further reduces the hardware requirements of address generation, but also makes the small area of memory space. (3) The implementation can be derived in a simple way with regular controlling circuitry. (4) The result can be easily applied to different applications of Viterbi decoder and the effectiveness of the developed techniques is very apparent for convolutional codes with a long memory order.