Study of Buck Fed Half-Bridge Converter With Synchronous Current-Doubler Rectification

• Main Authors: Chien-Ming Wu, 吳健銘
• Other Authors: Tsorng-Juu Liang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/46326151084117212302

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === 　　We have considered zero voltage switching(ZVS) operation of the buck fed half-bridge converter with synchronous current- doubler rectification and achieved ZVS in full load range. First, the basic operation principle of the symmetrical half converter with synchronous current- doubler rectification in different state is described in the thesis, and the ZVS operation, duty cycle loss and the effect of the circuit parameters are analyzed. The design consideration for ZVS in full load range is proposed. 　　A buck fed half bridge converter with synchronous current-doubler rectification with input voltage range 36~72V and 3.3V/50A output is experimentally performed. The maximum efficiency is 89.66%, which demonstrates the performance of the proposed technique.