| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === This thesis presents the research on CMOS integer-N frequency synthesizer RFICs for 2GHz and 5GHz 802.11 WLAN applications. The RFICs are fabricated in a TSMC standard 0.25um and 0.18um CMOS process. A switching capacitor mechanism is used in the design of VCO to change the capacitance of the LC tank to compensate the frequency deviation due to process variation. The circuit measurement is performed using a FR-4 PCB test fixture. The 5GHz 0.25-um CMOS VCO exhibits an output frequency from 4780 to 4943MHz (switch on) and 4877.3 to 5022.3MHz (switch off), respectively, and the phase noise is –85.6dBc/Hz@100KHz. The 5GHz 0.18-um CMOS VCO exhibits an output frequency from 4598.3 to 4723.7MHz (switch on) and 4739.3 to 4858.5MHz (switch off), respectively, and the phase noise is –86.4dBc/Hz@100KHz. The 2GHz 0.25-um CMOS VCO has an output frequency from 1808 to 1970 MHz with a phase noise of –95.1dBc/Hz@100KHz. The 5-GHz pulse-swallow counter (0.18um) exhibits a maximum operation frequency of about 5.5GHz. The 2-GHz pulse-swallow counter (0.25um) exhibits a maximum operation frequency of about 2.8GHz. Detail measurement and the frequency synthesizer performance problem is presented and discussed.
|
|---|
