A Low Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value approach
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === In this thesis, a 6-bit 300 MS/s flash ADC based on a novel Complementary Average-Value (CAV-Based) approach is proposed. Input signal is pre-processed and then compare with a fixed reference voltage level, which greatly simplifies the comparator design and...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98839606826471633225 |