| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === This thesis presents how to build a kernel which is based on micro-kernel architecture on a SOC of heterogeneous multiprocessors. The micro-kernel architecture is based on message-passing mechanism. There are four essential parts in the kernel, namely inter-process communication, hardware interrupt handler, inter-processor communication and scheduler. Message-passing between processes is the responsibility of inter-process communication. When a hardware interrupt is triggered, hardware interrupt handler must handle it. Inter-processor communication handles the communication between processors. Choosing next process to execute is scheduler’s duty.
The kernel described in this thesis has been implemented on a reference design of TI TMS320DSC25 which is a heterogeneous multiprocessors SOC containing a ARM7TDMI core and a C5409 DSP core. ARM7 is a general purpose processor with 32-bit capability, while C5409 is a digital signal processor with 16-bit capability. The ARM processor and the DSP processor run their own copy of the kernel independently. Except the hardware dependent functionality, the two copies of the kernel are designed with the same structure providing same service functions through the same application program interfaces.
By executing micro-kernel on DSC25, different processes executing on different processors can communicate or request services via inter-processor communication. Finally, every critical sections of the kernel, no matter whichever processor it running on, can complete in a bounded time.
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