| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === In this paper, we propose a new synthesis algorithm and a new cell library. At first, we modify the LEAP cell and call it as new LEAP cell. The new LEAP cell contains nY cells and cY cells. They have higher speed, lower power, and less area than the old ones. Logic functions have two kinds of characteristics: unite and binate. Based on these two characteristics, we use different logic styles to mapping logic functions. Hence, we find the functions in a BDD which are suitable for CMOS mapping. Then, replace the BDD of this function to a node and mapping to CMOS. Finally, we compose circuits which are mapping to PTL and static CMOS. The Experimental Results show that our approach has better performance and less area than conventional CMOS technology mapping.
|
|---|
