| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === Accurate measurement of jitter to picosecond accuracy using conventional methods requires very high-cost test instrumentation. In this thesis, we present a low-cost technique for jitter measurement of phase-locked loops (PLLs). The proposed approach exploits the high sensitivity of PLL’s jitter to power supply variations, and is applicable to PLLs whose jitter is predominantly due to power supply noise. The technique enables the potential of using of a medium-accuracy tester for the production test of PLL’s jitter.
The aim of this thesis is to develop an efficient methodology for analyzing jitter. Instead of describing the jitter in the traditional phase domain, we deal with the jitter directly in the defined “jitter domain”. In this manner, it becomes much more easier to observe and then analyze the behavior of jitter at the circuit-level simulation. After that a simple on-chip PLL’s jitter measurement circuit, which utilizes the jitter-domain principle, is proposed and demonstrated.
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