VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications

碩士 === 國立中興大學 === 電機工程學系 === 92 === Abstract As VLSI technology continues to improve, reconfigurable computing has opened new frontiers in the field of computer architecture. The disadvantage of AISC, less flexible and high cost, is inefficient to use. Our purpose, r...

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Main Author: 邱俊瑋
Other Authors: L.K Lai
Format: Others
Language:zh-TW
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/51797904003971724722
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spelling ndltd-TW-092NCHU04420842015-10-13T12:46:51Z http://ndltd.ncl.edu.tw/handle/51797904003971724722 VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications 可重組化計算引擎於多媒體應用之設計與實現 邱俊瑋 碩士 國立中興大學 電機工程學系 92 Abstract As VLSI technology continues to improve, reconfigurable computing has opened new frontiers in the field of computer architecture. The disadvantage of AISC, less flexible and high cost, is inefficient to use. Our purpose, reconfigurable architecture, can achieve both high performance of ASIC and the flexibility. Because reconfigurable hardware can map on different application, we re-use it only by re-configured. It is obvious to reduce design cost instead of ASIC, needed re-designed a new chip for different application. And reconfigurable hardware contained flexible function units and re-configured interconnect network. According to above, our purpose has more flexible than general purposed processor. In recently, there are many new reconfigurable architectures are investigated. This work proposed a new model of reconfigurable computing architecture. We developed to investigate the effectiveness of combining multiple reconfigurable function units for word level. Our purpose is a coarse-grain, integrated reconfigurable system-on-chip targeted at high throughput and data-parallel application such as video compression. It comprises an array of reconfigurable array (RC array), 2 instruction memories, 2 data memories and flexible interconnect network. In each function unit, it supports 3 stage pipeline and special instruction for butterfly algorithm, ex: DCT, FFT etc. The features of our purpose are clarified with emphasis on SIMD nature of RC array. Function unit (FU) can perform different word level, ex. 8-, 16-, 32-, 64- bits, arithmetic operation and 8-, 16- 32-bits multiplication. The extensive functional and interconnect re-configurability is described along with the illustration of its utility in efficiently executing a set of target application. Taking the advantage of the communication, reallocation and duplication of flexible interconnection networks, the reconfigurable computing engine can perform a lot of operations flexibly. It was in its infancy. We will enhancements on the system adaptability for different classes of applications in further. L.K Lai 賴永康 2004 學位論文 ; thesis 101 zh-TW
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language zh-TW
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sources NDLTD
description 碩士 === 國立中興大學 === 電機工程學系 === 92 === Abstract As VLSI technology continues to improve, reconfigurable computing has opened new frontiers in the field of computer architecture. The disadvantage of AISC, less flexible and high cost, is inefficient to use. Our purpose, reconfigurable architecture, can achieve both high performance of ASIC and the flexibility. Because reconfigurable hardware can map on different application, we re-use it only by re-configured. It is obvious to reduce design cost instead of ASIC, needed re-designed a new chip for different application. And reconfigurable hardware contained flexible function units and re-configured interconnect network. According to above, our purpose has more flexible than general purposed processor. In recently, there are many new reconfigurable architectures are investigated. This work proposed a new model of reconfigurable computing architecture. We developed to investigate the effectiveness of combining multiple reconfigurable function units for word level. Our purpose is a coarse-grain, integrated reconfigurable system-on-chip targeted at high throughput and data-parallel application such as video compression. It comprises an array of reconfigurable array (RC array), 2 instruction memories, 2 data memories and flexible interconnect network. In each function unit, it supports 3 stage pipeline and special instruction for butterfly algorithm, ex: DCT, FFT etc. The features of our purpose are clarified with emphasis on SIMD nature of RC array. Function unit (FU) can perform different word level, ex. 8-, 16-, 32-, 64- bits, arithmetic operation and 8-, 16- 32-bits multiplication. The extensive functional and interconnect re-configurability is described along with the illustration of its utility in efficiently executing a set of target application. Taking the advantage of the communication, reallocation and duplication of flexible interconnection networks, the reconfigurable computing engine can perform a lot of operations flexibly. It was in its infancy. We will enhancements on the system adaptability for different classes of applications in further.
author2 L.K Lai
author_facet L.K Lai
邱俊瑋
author 邱俊瑋
spellingShingle 邱俊瑋
VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
author_sort 邱俊瑋
title VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
title_short VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
title_full VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
title_fullStr VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
title_full_unstemmed VLSI Architecture Design and Implementation of Reconfigurable Computing Engine for Multimedia Applications
title_sort vlsi architecture design and implementation of reconfigurable computing engine for multimedia applications
publishDate 2004
url http://ndltd.ncl.edu.tw/handle/51797904003971724722
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