Design and Implementation of Frequency Synthesizer Circuitry for Wireless Communication

• Main Authors: Shao-Yu Li, 李紹宇
• Other Authors: C.C. Meng
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/36397118531016778505

碩士 === 國立中興大學 === 電機工程學系 === 92 === For the wireless communication industry developing rapidly in recent years, the component manufacturing technology becomes ripe for integrating analog and digital circuits to realize system on a chip (SoC) no longer out of reach. The following new challenge is the clock problems inside the chip, including clock synchronization, deskew issue, and frequency modulation etc. In view of this, all kinds of phase-locked loops circuits become the major focus in the circuit design, and high accuracy and multi-channel synthesizer are adopted by the industry extensively. In this thesis, we discuss the circuit chips’ design of frequency synthesizer which meets the need of the IEEE 802.11b/g standard specification for the RF Front-end environment. All chips are implemented by the TSMC’s 2P4M, 0.35um CMOS technology, and measured by the On-wafer techniques which provided by the NDL’s RF group. Moreover, we provide three different topologies of high speed Prescaler all constructed by Current Mode Logic Master-Slave DFF circuits , including 1.5 GHz Prescaler (divided-by-2), 2.4 GHz Prescaler (divided-by-4/5), and 2.4 GHz multi-modulus Prescaler ( divided-by-256~271). Finally, we propose a 2.4 GHz integer N multi-channel frequency synthesizer.