SDRAM Controller IP Design

• Main Authors: Yu-Cheng Lin, 林育正
• Other Authors: Chuen-Yau Chen
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/92316545511318074592

碩士 === 義守大學 === 電子工程學系 === 92 === A digital intellectual property of SDRAM controller with a wrapper compatible with the AMBA is proposed in this thesis. For the purpose of reusability, most of the control variables are parameterized that provides the high flexibility for controlling the SDRAMs with other specifications. The function of this design was simulated with ModelSim, Cadence, and Verilog-XL; the Verification Navigator was adopted to check the rules in Reuse Methodology Manual; logic synthesis was performed by Synopsys. The whole design was verified by controlling Micron 128-MB SDRAM MT48LC4M32B2. The simulation results show that this design performs well.