Programmable Arbiter Design for SoC Application
碩士 === 義守大學 === 電子工程學系 === 92 === In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priori...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31696095258507373392 |
| Summary: | 碩士 === 義守大學 === 電子工程學系 === 92 === In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain low latency in system performance is explained. The implementation of a programmable arbiter to increase the bandwidth utilization is proposed. The analysis of various combinations of the arbitration algorithms indicates a better performance can be achieved as compared with the traditional arbitration assignment scheme. The simulation results of the programmable arbiter are shown on Altera Max Plus II design environment and implementation in Altera EPF10K100ARC240-1 FPGA and verified in ARM AMBA University Kit (AUK) environment.
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