The Investigation and Implementation of Intellectual Property of Fast Fourier Transform

• Main Authors: Greg Tseng, 曾士賓
• Other Authors: Sung-Yuan Ko
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/62147205060647022008

碩士 === 義守大學 === 資訊工程學系 === 92 === The purpose of this research is to design a parameterize Intellectual Property (IP) of Fast Fourier Transform (FFT) with variable length. The number of points of the FFT can be set by the parameter. It can be used alone as a FFT processor or together with a microprocessor to build a SOC. We also designed a memory address generation unit (AGU), and used it to generate the sliding window. The overlap between the sliding windows is also control by a parameter. This parameter can control the responsiveness of the spectrum calculation. We have built a 256-points hardware FFT processor by using VHDL code. This processor is tested on the FPGA with special attention paid to trade off between the area and speed. In this paper we will introduce the theorem of FFT and describe the components in the FFT IP. We also discuss about the architecture of the IP and its verification.