VLSI Circuit <a href="http://www.ntsearch.com/search.php?q=Design&v=56">Design</a> of Fast Codeword <a href="http://www.ntsearch.com/search.php?q=Search&v=56">Search</a> Algorithm for Vector Quantization Based on System On Programmable Chip Design

• Main Authors: Shih-Chang Li, 李世璋
• Other Authors: Wen-Jyi Hwang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/tafsy7

碩士 === 中原大學 === 電機工程研究所 === 92 === To the encoder of vector quantizer, the most time-consuming part is codeword <a href="http://www.ntsearch.com/search.php?q=search&v=56">search</a>. Codeword <a href="http://www.ntsearch.com/search.php?q=search&v=56">search</a> includes a large amount of addition, subtraction, multiplication and logic operation. These will cause very high calculation complexity when calculated in the <a href="http://www.ntsearch.com/search.php?q=software&v=56">software</a>. It will spend a large number of <a href="http://www.ntsearch.com/search.php?q=time&v=56">time</a> for codeword <a href="http://www.ntsearch.com/search.php?q=search&v=56">search</a>. In this thesis, we present a <a href="http://www.ntsearch.com/search.php?q=hardware&v=56">hardware</a> architecture of fast codeword <a href="http://www.ntsearch.com/search.php?q=search&v=56">search</a> algorithm based on SOPC(System On Programmable Chip) <a href="http://www.ntsearch.com/search.php?q=design&v=56">design</a>, suitable for image encoding application based on vector quantization. This architecture integrates one specialized <a href="http://www.ntsearch.com/search.php?q=hardware&v=56">hardware</a> circuit includes operational accelerating function of vector quantizer codeword <a href="http://www.ntsearch.com/search.php?q=search&v=56">search</a> and Nios Embedded Processor System into one programmable chip. It is with high efficiency and integrated for the system. The specialized <a href="http://www.ntsearch.com/search.php?q=hardware&v=56">hardware</a> architecture that this thesis put forward has combined the Wavelet Transform and Partial Distance Search(PDS), includes the Haar DWT Unit, Distortion Calculation Unit, PDS Unit, Codebook ROM and Control Unit. We present a parallel processing architecture suitable for multi-modules in addition, and this reach more high-speed calculation under the accuracy of searching same as the <a href="http://www.ntsearch.com/search.php?q=single&v=56">single</a> module. We use Altera SOPC <a href="http://www.ntsearch.com/search.php?q=design&v=56">design</a> flow to implement the architecture of this thesis we present in the Cyclone EP1C20F400C7 device, and complete system verification and efficiency comparison in Nios platform. We can find that the operation efficiency of the architecture we present is superior to Pentium Ⅲ 1GHz and Pentium IV 2.4GHz microprocessor by the comparative result.