Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
碩士 === 中華大學 === 電機工程學系碩士班 === 92 === Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jit...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31763762251512462034 |