Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis

碩士 === 中華大學 === 電機工程學系碩士班 === 92 === Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jit...

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Bibliographic Details
Main Authors:	kai-chung-chang, 張凱鈞
Other Authors:	Jwu-E Chen
Format:	Others
Language:	zh-TW
Published:	2004
Online Access:	http://ndltd.ncl.edu.tw/handle/31763762251512462034

id	ndltd-TW-092CHPI0442022
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spelling	ndltd-TW-092CHPI04420222016-01-04T04:08:39Z http://ndltd.ncl.edu.tw/handle/31763762251512462034 Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis 時脈抖動模型與波形產生以模擬為基礎的品質分析 kai-chung-chang 張凱鈞碩士中華大學電機工程學系碩士班 92 Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jitter model and generating the clock waveform with clock jitter, so that the Simulation-based quality analysis can be approved. We can easier to find out the problem which in the system and effectively decrease the jitter variation. Jwu-E Chen 陳竹一 2004 學位論文 ; thesis 31 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中華大學 === 電機工程學系碩士班 === 92 === Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jitter model and generating the clock waveform with clock jitter, so that the Simulation-based quality analysis can be approved. We can easier to find out the problem which in the system and effectively decrease the jitter variation.
author2	Jwu-E Chen
author_facet	Jwu-E Chen kai-chung-chang 張凱鈞
author	kai-chung-chang 張凱鈞
spellingShingle	kai-chung-chang 張凱鈞 Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
author_sort	kai-chung-chang
title	Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
title_short	Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
title_full	Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
title_fullStr	Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
title_full_unstemmed	Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis
title_sort	clock jitter model and waveform generation for simulation-based quality analysis
publishDate	2004
url	http://ndltd.ncl.edu.tw/handle/31763762251512462034
work_keys_str_mv	AT kaichungchang clockjittermodelandwaveformgenerationforsimulationbasedqualityanalysis AT zhāngkǎijūn clockjittermodelandwaveformgenerationforsimulationbasedqualityanalysis AT kaichungchang shímàidǒudòngmóxíngyǔbōxíngchǎnshēngyǐmónǐwèijīchǔdepǐnzhìfēnxī AT zhāngkǎijūn shímàidǒudòngmóxíngyǔbōxíngchǎnshēngyǐmónǐwèijīchǔdepǐnzhìfēnxī
_version_	1718158864993484800

Clock Jitter Model and Waveform Generation for Simulation-Based Quality Analysis

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