| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === Recently, the trend of processor technology may not only pursue high performance and reduce the hardware design complexity but also consider the reliability and power issues. Therefore, high performance processor like VLIW, to contain power-effective fault-tolerant scheme, would be a fantastic idea. In this study, a power-effective fault-tolerant design framework of VLIW processor is proposed. Specifically, this paper concentrates on the issue of dependable data path design. We use three identical functional modules in the data paths to demonstrate our fault-tolerant technique with emphasis on power reduction. Basically, we add one spare module in this illustration and refine on the concepts of triple modular redundancy and comparison to achieve fault detection, fault location and error recovery. A concurrent error detection and real-time recovery process is developed to conquer the faults. Hardware architecture and its implementation in VHDL are developed. The hardware-emulated fault-simulation approach is used to estimate the fault coverage and power consumption. The comparisons of power consumption with previous fault -tolerant VLIW processor are conducted to validate our scheme.
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