| Summary: | 碩士 === 中華大學 === 資訊工程學系碩士班 === 92 === As VLSI technology reaches deep submicron or nano-meter dimensions, VLSI design has become more complicated. In physical design, more different goals will come out in the routing stage, for example interconnect delay, routability, signal integrity…etc.
Traditional routing stage in physical design can be separated into the global routing step and the detailed routing step. In general, the global routing partitions the entire routing plane into a 2-dimensional array of grids, and find one grid-to-grid path for each two-endpoint wire. However, the concept of grid-based global routing is inefficient. If the size of any partitioned grid is too large, some wires may be fully contained inside one grid cell so that the connection of wires is unable to be represented in the congestion estimation. If the size of any partitioned grid is too small, the computation time of each wire in the congestion estimation will increase. Hence, it is difficult to define one feasible partitioned grid size in the routing plane.
In this thesis, one hierarchical timing-constrained full-chip routing(HTFR) system is proposed to deal with modern routing issue. Considering the timing constraint of any wire, the entire routing plane can be partitioned hierarchically into different size grids for different routing requirement. Our HTFR system can be divided into four phases: (1) Top-down timing-constrained congestion-driven global routing(TCGR) in a quad-grid model, (2) Simulated-annealing-based timing-constrained rip-up-and-reroute(STRR) in a hierarchical quad-grid model and (4) Timing-constrained maze routing(TMR) in a routing plane. Our experimental results shows our proposed HTFR system can obtain 100% for many benchmark circuits.
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