| Summary: | 碩士 === 中華技術學院 === 電子工程研究所碩士班 === 92 === Based on the full-custom-design methodology and the principle of the phase-locked loop (PLL), this thesis presents the design of a frequency synthesizer operating over the band around 1.6GHz. The function blocks of the synthesizer include a phase-frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a delta-sigma modulator, and a frequency divider. With the .18µm CMOS technology provided by Taiwan Semiconductor Manufacturing Company (TSMC) as the design and simulation platform, this thesis presents the implementation a frequency synthesizer with the characteristics of low operating voltage, low power consumption, short locking time, and low phase noise.
The organization of the thesis is as follows: Chapter one provides an overview of the thesis, Chapter two discusses the contents of full-custom design methodology, Chapter three discusses the principle of phase -locked loop and the analysis method, Chapter four presents the architecture of the frequency synthesizer, Chapter five shows the details of the design of the frequency synthesizer. The last chapter concludes the thesis.
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