IP Design on Real-Time Edge Detection using FPGA
碩士 === 長庚大學 === 電子工程研究所 === 92 === This thesis describes a computational FPGA implementation for edge detection. A systolic array architecture has been examined for convolution operation, which benefits the design with simplicity and regularity. Moreover, most of the presented processing structures...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82298983959751899050 |