| Summary: | 碩士 === 長庚大學 === 電機工程研究所 === 92 === The intra-frame prediction is an important feature in the H.264/AVC standard, and it predicts the pixels of a block being encoded with the pixels in the neighboring reconstructed blocks. However, generating the predicted values for the pixels involves a very large amount of computation. For example, the luminance intra prediction contains nine 4x4 prediction modes and four 16x16 prediction modes, so 208 predicted values must be generated for predicting the pixel luminance in a small 4x4 block. It would require mass hardware to perform intra prediction in real-time.
This thesis deals with the architecture design of the intra-frame predictor. In the thesis, we first analyzed the data dependences between the predicted values of the pixels for various prediction modes. Then we designed our intra frame predictor based on the dependency analysis to eliminate redundancy computations. Hence, our design can achieve a better cost-performance ratio than previous works. Simulations show that our intra predictor can operate in 90MHz with power consumption of 8.4242 mW. The total gate count of our design is 12719.
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