The Realization of Symbol Timing Estimation for IEEE 802.11a Baseband Receiver and UART Interface Between PC and IEEE 802.11a Baseband Tranceiver

• Main Authors: Chun - Wai Chang, 張浚瑋
• Other Authors: Tsung - Hsien Liu
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/48030012183691579771

碩士 === 國立中正大學 === 通訊工程研究所 === 92 === The major work of this thesis is to study the timing synchronization of an orthogonal frequency division multiplexing (OFDM) IEEE 802.11a baseband receiver ， both from the theoretical and implementational perspectives, and hardware interfacing between PC and FPGA emulation board 。 Note that the timing synchronization discussed in this thesis includes packet synchronization and symbol synchronization 。 For an IEEE 802.11a baseband receiver, the sequence of functions after the analog-to-digital converter include packet synchronization ， frequency synchronization, and symbol synchronization 。 The work of symbol synchronization is to find the starting point of every OFDM symbol 。 The symbol synchronization algorithm discussed in this thesis calculates the cross-correlation between the received signal and already-known cyclic prefix (CP) 。 The time instant where the cross-correlation is largest is determined to be instant where an OFDM symbol starts 。 The results from hardware implementation of the algorithm is shown to be close to those from by MATLAB simulations 。The hardware realization of UART interfacing between PC and FPGA emulation board is also reported 。