| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 92 === With the advances of technologies in multimedia and communication, network, photographs, and video films are used in many applications. And we have known that the Variable Length Code (VLC) is the most popular loss-less compression technology in JPEG, MPEG, H263, and so on. Therefore, a high throughput data rates VLC codec system with smaller memories would be an important topic.
In this work, we investigate the architecture and circuit optimization of VLC codec system based on the Shieh’s work on 2001[1], and the concept of Content Addressable Memory (CAM) with novel circuit design was introduced into our work. Besides, the integration of CAM and RAM and the prioritized group-based algorithm also boots out performance, reduce the area cost and power consumption.
The proposed VLC codec system was implemented using 0.18um process and occupies an area of 1.626mm*1.626mm. This implementation achieves the throughput rates up to 389MHz at a 389MHz clock rate and takes 223mW in power consumption.
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