Mutation Coverage Estimation for Symbolic Model Checking

碩士 === 國立中正大學 === 資訊工程研究所 === 92 === When people design a system, there is always a question about how exhaustive the system has been examined to be right. Coverage estimation provides an answer to this question in simulation. A model checker verifies a design exhaustively, and proves the...

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Main Authors: Te-Chang Lee, 李德昌
Other Authors: Pao-Ann Hsiung
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/73344078156887096871
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spelling ndltd-TW-092CCU003920742016-01-04T04:08:29Z http://ndltd.ncl.edu.tw/handle/73344078156887096871 Mutation Coverage Estimation for Symbolic Model Checking 符號式模型檢驗的改變式涵蓋率評估 Te-Chang Lee 李德昌 碩士 國立中正大學 資訊工程研究所 92 When people design a system, there is always a question about how exhaustive the system has been examined to be right. Coverage estimation provides an answer to this question in simulation. A model checker verifies a design exhaustively, and proves the satisfaction of specifications. However, people have noticed that errors exist even after verification is done. In recent years, formal techniques set feet to this field for the same reason "\How complete is the formal verification once done?". We proposed an intuitive way to estimate the completeness of formal verification. Once a system satisfies a specification, we estimate the coverage of completeness for a set of properties by applying some mutations to a system model and calculate its relevance to the given properties. Several mutation models are employed to exploit the estimation. Our experience on some real cases will demonstrate how our methodology helps verification engineers to find the uncovered hole. Pao-Ann Hsiung 熊博安 2004 學位論文 ; thesis 75 en_US
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description 碩士 === 國立中正大學 === 資訊工程研究所 === 92 === When people design a system, there is always a question about how exhaustive the system has been examined to be right. Coverage estimation provides an answer to this question in simulation. A model checker verifies a design exhaustively, and proves the satisfaction of specifications. However, people have noticed that errors exist even after verification is done. In recent years, formal techniques set feet to this field for the same reason "\How complete is the formal verification once done?". We proposed an intuitive way to estimate the completeness of formal verification. Once a system satisfies a specification, we estimate the coverage of completeness for a set of properties by applying some mutations to a system model and calculate its relevance to the given properties. Several mutation models are employed to exploit the estimation. Our experience on some real cases will demonstrate how our methodology helps verification engineers to find the uncovered hole.
author2 Pao-Ann Hsiung
author_facet Pao-Ann Hsiung
Te-Chang Lee
李德昌
author Te-Chang Lee
李德昌
spellingShingle Te-Chang Lee
李德昌
Mutation Coverage Estimation for Symbolic Model Checking
author_sort Te-Chang Lee
title Mutation Coverage Estimation for Symbolic Model Checking
title_short Mutation Coverage Estimation for Symbolic Model Checking
title_full Mutation Coverage Estimation for Symbolic Model Checking
title_fullStr Mutation Coverage Estimation for Symbolic Model Checking
title_full_unstemmed Mutation Coverage Estimation for Symbolic Model Checking
title_sort mutation coverage estimation for symbolic model checking
publishDate 2004
url http://ndltd.ncl.edu.tw/handle/73344078156887096871
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