| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 92 === Nowadays, the main data presentation of video is in digital form. As the development and requirements of the multimedia technologies and applications grows, a large mount of data is required to be stored and transmitted. Therefore, the digital data are compressed into bitstream according to the popular MPEG video compression techniques for efficient storage and communication. With respect to different video coding standards, the syntax of bitstreams are also different. So, to parse Multi-MPEG bitstreams efficiently is an important issue to meet real time requirements in various video applications.
In this thesis, we propose a Multi-MPEG Bitstream Processing IP core. For achiecing both high performance and low power purposes, we propose a “Fast Aligning Response Shift (FARS)” approach in handling the bitstream parsing efficiently. Based on the UMC 0.18μm CMOS technology, we finish the proposed design in terms of behavioral simulation through C-language modeling, RTL modeling through Verilog, gate-level modeling through Synopsys and FPGA realization through Xilinx ISE. We find that the optimal working frequency in the proposed design achieves 65MHz. As compared with other designs, the proposed design not only outperforms others in terms of less hardware cost and higher processing speed, but also possesses much less power consumption than others (i.e. reducing 72% power consumption). The result of comparisons shows the good performance of the proposed design.
About IP qualification of the proposed IP core, we use NOVAS nLint Code Checking tool to examine the RTL code, ModelSim CodeCoverage tool to examine the code coverage rate of the provided testbench, and Synopsys Formality tool to examine the formal functional verification. In addition, we also complete the system verification and FPGA verification of the proposed IP core.
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