Adaptive way configurable architecture for low power cache

• Main Author: 崔志強
• Other Authors: 陳添福
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/44078928277872530410

碩士 === 國立中正大學 === 資訊工程研究所 === 92 === Microprocessor performance has been improved by increasing not only the size of on-chip caches but also the way set-associative of on-chip caches. However, that increases the total power consumption. When the increasing of use of portable computing systems. Power consumption also becomes an important design consideration for microprocessor. Static power consumption becomes more and more important. So the recent year, some researches begin focus on static power reduction. One of those researches is AMC cache. AMC cache is the better method of the present researches, because AMC cache reduces static power consumption while maintaining high performance. But dynamic power consumption still dominates the L1 cache power consumption for a 0.13um technology. In this paper, we present our method to reduce dynamic power consumption. We attach our method on AMC cache. We name our method as adaptive way configuration cache (AWC cache). When a cache access occurs, we use pre-stored information of the cache set to know the set-associative of the cache set. The pre-stored information can let us know that we need to access four ways or only two ways. We also use cache block turn off information to know which way does not need to be used. We reduce the number of active ways on each cache access, so we can save dynamic power consumption. Simulation results show that our method can efficient save dynamic power consumption.