The Research on the Reliability of MOS Capacitor of High-k HfO2 Ultrathin Film Deposited on Different Substrates

• Main Authors: Chia-wei Wu, 巫家瑋
• Other Authors: Hsueh-Tao Chou
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/63475476208632377272

碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 === As the device dimension was scaling down, high mobility substrate and high dielectric oxide are attracting great interest as a replacement for silicon-based devices. Among the many candidate materials, HfO2 has been highlighted due to its good device characteristics. Besides, Ge substrate has been considered because it has demonstrated higher low-field carrier mobility and smaller mobility bandgap, therefore, we attempt to demonstrate MOS capacitors on Ge with HfO2 gate dielectrics in comparison with the silicon-based capacitors. The initial goal of the work is to focus the reliability of the high-k material and different substrate as well as the mechanism of trapping transient effects. The new modeling is attempted and developed to explore the traditional viewpoint based on the measurements of I-V and C-V data. In this thesis, we will emphasize on the fabrication of HfO2 thin films. HfO2 was deposited on Si and Ge wafer respectively using R.F. magnetron sputtering with the Ar+O2 modulation techniques, and then we use different annealing temperature treatments in furnace. Finally, we deposited Al film as top and bottom electrode, the MOS capacitor structure was fabricated. The characteristics and qualities of MOS capacitors were analysed and compared with different annealing temperature conditions by I-V and C-V measurements. Based on the experimental results, we found that both the capacitor structure on Si wafer and Ge wafer at 450℃ annealing temperature condition, the characteristics in equivalent oxide thickness (EOT), dielectric constant, hysteresis and leakage current were better than the other annealing temperature conditions. In constant current stress condition, the trapping behavior in the dielectric has been proved to be the hole trapping. The future work will still make an effort on the optimum conditions of fabrication from analyzing the above mechanisms, then to fabricate the Ge-MOSFETs with the ultra-thin high-K dielectric using low thermal budget process and to demonstrated the difference of conduction mechanisms between the silicon- and germanium-based memory devices.