| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 === The Viterbi algorithm, widely used in digital communications, is known to be an efficient method for the realization of maximum likelihood decoding of convolutional codes. Of the key techniques to successfully designing the Viterbi decoders, how to efficiently manage the path metric memory unit (PMMU) and at the same time to minimize the interconnection networks between PMMU and add_compare_select unit (ACSU) is always a key concern of hardware implementation.
In this thesis, we first derive a systematic method for conflict-free address arrangement of in-place path metric update according to the butterfly-based computation. In this manner, we can increase the equivalent memory bandwidth at the expense of more complicated interconnects. To further reduce the interconnect overhead, we present a novel and efficient in-place scheduling technique, denoted as the extended in-place scheduling, such that every ACSU will only access a dedicated, partitioned memory bank; therefore, the interconnection network is simplified and the bank becomes conceptually local to the specific ACSU.
The resulting architecture has the following characteristics: (1) The whole memory can be systematically partitioned into several sets of banks and each set can be treated as a local memory of a specific ACSU. (2) The implementation can be derived in a simple way with regular controlling circuitry (3) The result can be easily applied to different applications of Viterbi decoder and the effectiveness of the developed techniques is very apparent for convolutional codes with a long memory order. Finally, to show the resulting performance, we apply the presented techniques to both DAB (4, 1, 6) and CDMA (3, 1, 8) systems and demonstrate the flexibility of our development.
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