| Summary: | 碩士 === 國立雲林科技大學 === 電子與資訊工程研究所碩士班 === 91 === With the advent of communication system, how to obtain a precise frequency is very important to us. So we need to design a frequency synthesizer that is capable of tuning quickly, in small frequency steps, over a wide frequency range. In this thesis, our target was to construct a fast-switching speed and high-resolution frequency synthesizer. In order to obtain a better frequency resolution, we didn’t use the traditional frequency synthesizer architecture, the PLL, and chose the direct digital synthesizer (DDS) to realize our synthesizer. In this dissertation, an efficient VLSI architecture design for direct digital frequency synthesizer algorithm is proposed based on recursive trigonometric function. It only employs two multipliers, two adders, a small ROM table, and a counter to generates16-bit cosine and sine outputs. Comparing to the existing design approaches, our architecture design has the advantages of low-cost and higher performance. In addition, both output waveforms can achieve 100dBc. The proposed architecture has been implemented in TSMC 0.35-μm 1p4m CMOS process technology. The chip layout size is 0.38μm2 and it working frequency is 70MHz with power consuming 1.63mw.
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