DESIGN AND IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD CHIP

• Main Authors: Cheng-hong Hsieh, 謝正洪
• Other Authors: Yaw-Fu Jan
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/83951116859290358972

碩士 === 大同大學 === 電機工程研究所 === 91 === In this thesis, we present a chip of the encryption and decryption with 128, 192, and 256 bits of keys based on the AES (Advanced Encryption Standard) algorithm. It deals with the data of 128 bits, and it can connect to computer through USB to complete the work of the encryption and decryption. The AES can be used in variety of Electronic Funds Transfer applications as well as other electronic banking and data handling applications where data must be encrypted. To realize the chip of this design, we use VHDL, Xilinx tool and Synopsys library to design and simulate. We use FPGA(XCV 1000E-08-HQ240 0.18μm CMOS process, 3.3V power supply) to implement it. The gate count is 130,435. The operating clock rate is 14.8MHz. Data throughput is about 45.1Mbit/sec.