| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 91 === Delta-sigma converter provides a higher resolution for narrowband (<200kHz) signals at traditional super-heterodyne receiver. However, this traditional receiver structure suffers from the analog non-idealities such as I/Q path mismatch and low-frequency noise. Bandpass delta-sigma converter performs digitization at the super-heterodyne receiver IF stage to avoid those non-idealities. Furthermore, as it performs channel-select filtering in digital domain, there are several advantages, such as, the ease of programming channel-select filtering that will increase multi-standard adaptability, thus increasingly lower the cost in terms of area and power consumption due to the even shrinking of the dimension and the decrease of the supply for digital CMOS technologies.
This thesis proposes a double-path architecture for a 4th-order, bandpass modulator that is based on the use of switched-capacitor biquadratic filters. Two interleaved paths clocked at 21.4 MHz digitize a 200 kHz bandwidth signal centered at 10.7 MHz. The circuit is implemented by TSMC 0.25-μm 1P5M CMOS process, and it is expected to achieve a peak SNR of 59.3 dB with occupying 466μm×260μm layout area and less than 22mW power consumption at 2.5 V supply. The proposed modulator is designed with top-down design manner. The Delta-Sigma Toolbox for MATLAB and SIMULINK are used for defining a valid building block specifications; HSPICE is used for the transistor-level simulations; Cadence composer for the physical-level layout.
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