Design of Integrated Circuit for Pulse-Width Modulation Controller
碩士 === 國立臺北科技大學 === 電機工程系碩士班 === 91 === This objective of this thesis is to design an Integrated Circuit (IC) for Pulse-Width Modulation (PWM) controller. The PWM techniques realized by the designed IC include deterministic and random switching techniques for three-phase space vector modulation, two...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20478086068353892554 |
| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系碩士班 === 91 === This objective of this thesis is to design an Integrated Circuit (IC) for Pulse-Width Modulation (PWM) controller. The PWM techniques realized by the designed IC include deterministic and random switching techniques for three-phase space vector modulation, two-phase space vector modulation, and new random space vector modulation. All techniques are based upon the symmetrical sampling method, which samples regularly the fictitious modulating signal every carrier period to give symmetrical PWM waveform in a carrier period.
The designed PWM controller is developed using VHDL and preliminarily verified by the Electronic Design Automation (EDA) software for TSMC 0.25m manufacturing process. It is further verified by the Field Programmable Logic Array (FPGA). The experimental results derived from the FPGA-based system and EDA tools confirm the design.
The designed IC is being taped off by TMSC using the manufacturing process of one poly layer and five metal layers. The chip size is 1660 um 1660 um and its clock rate and power dissipation are 10 MHz and 12.5 mW, respectively.
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