The Design and Implementation of Low Voltage CMOS Delta Sigma Modulators

• Main Authors: Chien-Hung Kuo, 郭建宏
• Other Authors: Shen-Iuan Liu
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/96642470419186673701

博士 === 國立臺灣大學 === 電機工程學研究所 === 91 === With rapid growth of the marketing in the portable electronic products, there is a strong demand for developing low voltage and low power circuit technique to increase the system level integration density and prolong the battery lifetime. Fortunately, the continued scaling on the VLSI technology leads to the reduction of the supply voltage, and it is also beneficial for the scaling of the battery size and weight. The reduced supply voltage results in the power saving in digital circuits, but complicates the design of high resolution analog circuits. In addition, the resulted power dissipation in analog circuit is not proportional to the lowered supply voltage as expected. It is a great challenge to maintain the desired performance of the AD converter while the supply voltage is reduced. Delta sigma (ΔΣ) modulators are insensitive to the imperfections on the analog components such as the device mismatch and amplifier gain, which are especially important for the low voltage applications. This scheme is well suitable for the realization of a high resolution, accuracy and narrow band analog-to-digital (AD) converter in audio and telecommunications applications. They also have the advantage of relaxing the requirements of the analog anti-aliasing filters in the AD converters. On the other hand, there is no significant power consumption and noise penalty for the AD conversion of the ΔΣ modulator in IF band. In this thesis, three low voltage ΔΣ modulators were explored and fabricated in the standard 0.25µm CMOS 1P5M process for the audio and FM receiver applications. First, a 1V nested-chopper second-order ΔΣ modulator is proposed to reduce both the flicker noise (1/f noise) and residual noise. The input dynamic range of the modulator is 69 dB with a bandwidth of 22.05kHz and a sampling rate of 2.5MHz. Second, a 1V second-order ΔΣ modulator using a single opamp is presented to reduce the area occupied and save the power dissipated. The maximum SNDR of the modulator is 68 dB with a audio bandwidth of 22.05kHz and a OSR of 64. Third, a 1V fourth-order bandpass ΔΣ modulator with double-sampling technique is proposed to reduce the sampling rate and the power consumption for the low voltage FM receiver applications. The maximum SNDR of the modulators is 60 dB within a bandwidth of 200kHz. The sampling rate of the modulator is 7.13MHz with a power consumption of 8.45mW.