| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 91 === Abstract
There are many applications about PLL and DLL circuit, such as wireless communication, control, embedded system, chip design, network communication…etc. Generally on theory, that is used to synthesize with unknown signal, and to multiply frequency and phase lock, then output different frequency as same phase signal, further more it could control the delay signal to make CPU speed up, but right now the DLL and PLL circuit is very difficult.
We study many research papers and patents, the input-signal does not processed in practical, just focus on the Phase lock of the Input and Output Signal. Not only data delay but also clock delay will propagate in the really world, and each data delay will be difference. So we should care of the clock and all signals. In the analog world, Filter/ Demodulator / Carrier/ Signal processing’s data un-integrity and delay will happen in the really world. Cause this reason, Lab. 202 show a new method to improve this problem.
In this paper, some method isn’t the standard rule like open loop control. We use this rule to multiple the frequencies, and the result is nice. The lock time and the jitter are satisfied in the IC design. Used this open loop control method, we can design the DLL circuit and the performance is near the limited of the semiconductor margin. I think we are the first one to implement the phase lock loop circuit in the FPGA. We don’t try to overturn the rule of PLL design, but try to use another method to solve the problem.
Hope this paper has some usefulness for the IC design.
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