The Theory and Design of 5GHz CMOS Phase-Locked-Loops Prescaler

• Main Authors: KUO CHIA-YUNG, 郭加泳
• Other Authors: 呂學士
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/29719566167614755839

碩士 === 國立臺灣大學 === 電機工程學研究所 === 91 === Phase-locked loops (PLL) are used extensively in communications systems, such as frequency synthesizers and clock recovery circuits. A frequency synthesizer generates a new frequency from a single stable reference frequency. Mostly a crystal oscillator is used for the reference frequency. Most of the frequency synthesizer employ a Phase Locked Loops circuit, as this technique offer many advantages such as minimum complex architecture, low power consumption and a maximum use of Large Scale Integration technology. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter. One approach to this necessity could be to use crystal oscillators. The main benefit of using Phase Locked Loop technique in frequency synthesizer is that it can generate frequencies comparable to the accuracy of a crystal oscillator and offer other advantages. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter, we use Source Couple Logic (SCL) architecture as D Filp-flop for 16/17 prescaler design, and thus to reduce the PLL side-band spurs. Considering the scope of this single circuit, this Thesis is devoted to the research of a digital PLL frequency synthesizer. Phase locked loop is an excellent research topic as it covers many disciplines of electrical engineering such as Communication Theory, Control Theory, Signal Analysis, Noise Analysis, and Design with transistors. At the end of this thesis, we present a 128/129 prescaler schematic and simulation results.